Devices or semiconductor elements are mounted on wiring boards. In recent years, these wiring boards are increasingly expected to be thinner and lighter and to have a higher density, in response to increased demands for smaller, thinner, and higher-density electronic devices and in response to an increase in the number of terminals of semiconductor elements along with advancement of the speed and function thereof.
Conventionally, a wiring board having through holes is common such as a build-up board. However, such board is thick and not desirable for high-speed signal transmission because of the through holes. Further, while a thin-type substrate such as a tape substrate is used as a wiring board, the manufacturing method thereof limits the number of wiring layers in the wiring board to one or two. In addition, since the tape base material has large elasticity, positional accuracy of the pattern is less than that of a build-up board. Thus, recent demands for a higher density cannot be met.
In response to these problems regarding wiring boards, there are proposed coreless substrates having no through holes. These substrates are formed by forming a wiring structure or the like on a prepared supporting substrate and removing or separating the supporting substrate. For example, Patent Document 1 discloses a technique of obtaining a wiring member including build-up wiring layers, as a coreless substrate. According to this document, an underlying layer and a metal foil are arranged on a prepreg that is used as a supporting substrate, and build-up wiring layers are formed on the metal foil. Subsequently, the circumferential part of the underlying layer is cut off to separate the metal foil. Patent Document 2 discloses a technique of obtaining a semiconductor device having circuit elements on a coreless substrate. According to this document, a multilayer wiring structure is formed on a metal foil used as a supporting substrate, and after circuit elements are mounted on the multilayer wiring structure, the metal foil is removed by etching. Patent Document 3 discloses a technique of obtaining a semiconductor device, by forming a first wiring layer on a supporting substrate, mounting a semiconductor element on a surface of the first wiring layer, removing the supporting substrate, and forming a second wiring layer on the surface opposite to the above surface of the first wiring layer.
While it is often the case that stress is caused by a difference in the thermal expansion coefficient between a wiring board and a semiconductor element mounted thereon, countermeasures against such stress are demanded. For example, Patent Document 4 discloses a construction that relaxes stress caused between a semiconductor element and a multilayered wiring board by a metal column arranged between terminals.
Patent Document 1:
    JP Patent Kokai Publication No. JP2007-158174APatent Document 2:    JP Patent Kokai Publication No. JP2004-200668APatent Document 3:    JP Patent Kokai Publication No. JP2006-294692APatent Document 4:    JP Patent Kokai Publication No. JP2001-196496A